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Development of pixel readout integrated circuits for extreme rate and radiation

Scritto da  Lunedì, 08 Luglio 2013 09:48


A dedicated pixel simulation and verification environment is currently under development for the performance analysis and optimization of alternative pixel readout chip architectures for next generation high energy physics experiments. Automated verification functions will be part of such a framework to enable extensive simulations of large sets of pixel hits and triggers to be performed in an automated fashion for global architecture evaluations and for all incremental extensions and refinements of a final design.


  • The CMS (Compact Muon Solenoid, ) hybrid pixel detector is one of the large general purpose experiments in the LHC (Large Hadron Collider) located at CERN. For its Phase 2 upgrade, which will take place during the next decade, not only will the luminosity and pileup drastically increase (5 x 1034 cm-1s-1), but also the trigger rates will necessarily increase as the experiment will grapple with triggering on high pileup events. This opens critical design challenges on the integrated circuit design: i) smaller pixels to resolve tracks in boosted jets, ii) much higher hit rates (1GHz/cm2), iii) unprecedented radiation levels (10 MGy) with increased risk of radiation induced single event upsets, iv) much higher output bandwidth, v) and large IC format with low power consumption. Such requirements will be addressed by adopting a 65nm CMOS technology.
  • Such a simulation and verification framework will be a highly valuable development and verification tool also for other high energy physics pixel detector systems and ASICs in general. A tool to make such a simulation and verification framework with sufficient versatility is the HDVL (Hardware Description and Verification Language) SystemVerilog combined with the UVM (Universal Verification Methodology) library, which is used for creating dynamic and reusable testbenches. Such tools enable simulations at both very high level and detailed gate level and are now widely adopted in the industry. A detailed SystemVerilog model of the pixel ASIC can be synthesized directly into digital gates in the chosen technology using multiple synthesis tools from all the major CAD tool suppliers.

This activity is part of the RD53 RD Collaboration “Development of pixel readout integrated circuits for extreme rate and radiation” between the ATLAS and CMS experiments. Instiutes and laboratories participating to the collaboration: INFN and Politecnico di Bari, Physikalisches Institut der Universität Bonn (Germany), CERN (Geneva, Switzerland), CPPM (Marseille, France), Fermilab (Chicago, United States), LBNL (Berkeley, Unites States), LPNHE (Paris, France), NIKHEF (Amsterdam, Netherlands), University of New Mexico (United States), University of Padova, University of Pavia and Bergamo, INFN and University of Pisa, INFN and University of Perugia, Paul Scherrer Institut (Switzerland), Rutherford Appleton Laboratory (United Kingdom), University of California Santa Cruz (United States), INFN and University of Torino.

Letto 259191 volte Ultima modifica il Martedì, 11 Marzo 2014 12:36